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Time for eDRAM! Ok, this process doesn't support eDRAM. Also, I don't understand the SRAM scaling failure here and I don't know if it would apply to eDRAM too. But it's something to think about given the increasing importance of wire delay.


I'm not sure you are serious, but eDRAM isn't a direct replacement for SRAM. At best it's useful for L3 or L4 cache given the inherently higher latencies.

I think we just have to accept that silicon scaling is slowing down.


I was assuming last level cache would be the majority of the usage in this case. Maybe I'm wrong.


For a desktop CPU that wouldn't be far off, but the A14 has a lot of other stuff so I very much doubt that. However, until we see an actual floor plan this is all speculation.


On the recent IBM z processors, eDRAM is used even for the L1 chip. And that's above 5GHz.


Thanks, I stand corrected!

Isn't eDRAM an IBM-only technology?




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