The theoretical maximum density is probably based on some type of physical law or just a simplified model.
That is often what people talk about when they talk about theoretical maximums/minimums.
Like if you have a box of dimensions 10x10x10cm the theoretical maximum number of dice of dimension 1x1x1cm you can fit in the box is 1000 dices.
Chances are you won’t get 1000 dices in to the box as the world is more complex than the theoretical model we used for the scenario.
Which is why if you want to build a box that holds 1000 dice, you need to take into account the +/- tolerances in your build process. At a guess, you'd probably want to build at something like [dimensions] + 2*[tolerance]. So if your build process produced a 10cm cube with +/- 1mm, you'd want to build a 10.2mm cube so even a worse-case -1mm tolerance issue you'd still have +1mm of and so still be able to get the dice in without using force. And assuming the dice themselves didn't have some crazy high tolerance ranges.
I've got a side-gig/hobby making stuff, and the the 2x tolerance works pretty well as a rule of thumb for me, but the project type, material, and application probably play a big part in those considerations. Any industrial/mechanical/materials engineer care to weigh in?
Time for eDRAM! Ok, this process doesn't support eDRAM. Also, I don't understand the SRAM scaling failure here and I don't know if it would apply to eDRAM too. But it's something to think about given the increasing importance of wire delay.
I'm not sure you are serious, but eDRAM isn't a direct replacement for SRAM. At best it's useful for L3 or L4 cache given the inherently higher latencies.
I think we just have to accept that silicon scaling is slowing down.
For a desktop CPU that wouldn't be far off, but the A14 has a lot of other stuff so I very much doubt that. However, until we see an actual floor plan this is all speculation.
